Anybody want to try reproducing a Vivado simulator bug?https://forums.xilinx.com/t5/Simulation-and-Verification/Reproducible-segfault-in-XSIM-with-malformed-function-call/td-p/811385 …
Verific actually accepts that input file. (Produces no error.) Not sure if that's because I'm running Verific in synthesis mode (where it ignores $display statements).
-
-
Try initializing an output reg to the function's value or something?
-
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.