@oe1cxw could you shed any light on this? https://github.com/mattvenn/memrd-problem … #yosys memrd
You can't connect a reg to an output port. Iverilog produces an error for this. Yosys produces exactly the circuit you have asked for: A driver-driver conflict between a memory and your adc module. (The conflict is then resolved by the bram mapper disconnecting adc data.)pic.twitter.com/in76bol0nD
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thanks Clifford. So far I've only been using iverilog for test benches and never run it on top.v. I wonder how many other warnings I've missed out on!
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