Asynchronous resets are bad design practice. Reset your flops synchronously or not at all.https://twitter.com/iowahawkblog/status/932309842123022336 …
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There are a few ways to do that. Would need to look up the exact sdc syntax, but it is possible. If you are worried about getting it right in combined STA, you can always re-run STA with 2nd set of rules with everything in slow clock domain.
But if you manage to cleanly switch between different clock speeds without a risk of clock glitches, and manage to verify statically that you did that correctly, then setting up STA for slower constraints on reset edges is easy in comparison.