Asynchronous resets are bad design practice. Reset your flops synchronously or not at all.https://twitter.com/iowahawkblog/status/932309842123022336 …
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Async reset tree = separate clock domain, and yes it is synthesized for another (slow) clock. Sync reset tree is part of main clock domain, so has to be synthesized together, for the fastest clock that circuit targeting.
You can specify different timings for different source-sink pairs for STA in every decent STA tool.
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Even more Blood, sweat and tears
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It's late and I'm going to bed now.. Not sure what you are trying to accomplish here tbh. I stated from the get go that I'm willing to die on that hill. ;) Good night my friend.
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