Asynchronous resets are bad design practice. Reset your flops synchronously or not at all.https://twitter.com/iowahawkblog/status/932309842123022336 …
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Sync reset tree need to be synthesized at Fmax of main clock. Tree has high fan-out and spans big distances. At high Fmax that means over-buffering + over-pipelining. Means big area / power overhead.
All that is also true for async clock tree because you have to release synchronously. If you only reset with slow clock (as you described in other tweet) then your sync reset tree does not need to be synthesized for Fmax. This is a strawman. Has nothing to do with sync vs async.
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Async reset tree = separate clock domain, and yes it is synthesized for another (slow) clock. Sync reset tree is part of main clock domain, so has to be synthesized together, for the fastest clock that circuit targeting.
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You can specify different timings for different source-sink pairs for STA in every decent STA tool.
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