Asynchronous resets are bad design practice. Reset your flops synchronously or not at all.https://twitter.com/iowahawkblog/status/932309842123022336 …
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Also: sync reset tree (being part of the same clock domain) becomes a part of critical path during the timing closure of high speed designs. Ability to exclude async reset tree from timing closure is big plus. IMHO
OH NO! You *have* to release an async reset synchronously! Otherwise you release reset in different cycles for different FFs and/or get metastability issues! Excluding async reset from timing closure is exactly as safe as excluding sync reset from timing closure: It isn't!
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Noop. Timing closure of async reset tree is done for different (very slow) clock. You do reset only when you switch-on power/voltage domain. So you can gate main domain clock or switch on slow clock, do reset, then ungate / switch to the faster clock.
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Fair enough. I haven't said that it is impossible to make correct designs with async resets, just that it's harder than most people think. Having a complex reset sequence as you described is one way. But most designs using async resets don't do any of that.
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