Asynchronous resets are bad design practice. Reset your flops synchronously or not at all.https://twitter.com/iowahawkblog/status/932309842123022336 …
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Why is resetting to a runtime value propagated from another reg worse? Is it because a constant will not cause metastability, but a runtime value could due to setup/hold issues when the reset edge arrives?
Has nothing to do with metastability. FFs have S and R inputs, not reset-enable and reset-data, so there's logic combining your reset signal and reset-data signal to generate S and R inputs for the FF. This logic must then be glitch free (aka "Hazzard Free", look it up).
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Interesting (to me anyway) aside: The SiliconBlue primitives library doesn't provide FFs with _both_ S and R inputs usable at the same time. I know what glitches are, don't worry :P. Should prob play w/ yosys to see what you mean about impl, however.
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Neither does Xilinx. If you code one in your HDL code, Vivado will create a circuit with two FFs, one async cleared and one async preset, a latch that remembers the last async event, and a mux that selects one of the FFs. Try it and look at the synthesis results. It's horrible.
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