Asynchronous resets are bad design practice. Reset your flops synchronously or not at all.https://twitter.com/iowahawkblog/status/932309842123022336 …
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How do you do resets for clock gated subsystems?
One (!) single (!) asynchronously reset flop that activates reset generator that will reset the circuit synchronously with the first clock edge when the clock is enabled, preferably by instantiating the FF primitive (no inference, like you'd also do for the clock gates).
