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Asynchronous resets are bad design practice. Reset your flops synchronously or not at all.https://twitter.com/iowahawkblog/status/932309842123022336 …
Also: If you reset asynchronously, for God's sake reset to a constant. If you reset to a runtime value you rely on glitch free synthesis. Glitch free synthesis is pretty much an open research topic, assuming your tool will just do the right thing in this case is insanity.
for fault tolerance you might want asynchronous reset entry with synchronous resume.
I use this often for push button resets.
How do you represent async resets in Verilog without using primitives since synthesizers only allow regs to be part of a single sensitivity list _IIRC_
A well written paper on this subject: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf …
How do you do resets for clock gated subsystems?
One (!) single (!) asynchronously reset flop that activates reset generator that will reset the circuit synchronously with the first clock edge when the clock is enabled, preferably by instantiating the FF primitive (no inference, like you'd also do for the clock gates).
Yep! I learned this the hard way with a very early design for my Kestrel-2 (circa 2007).
In FPGA's I agree but I'm not huge on "don't ever" in general, asynchronous resets have their place sometimes. In FPGA's they'll only cause issues but in ASIC's they can be very helpful for mixed-signal design with random timing.
I prefer asynchronous assert, sync release. Works in the absence of a clock and Xilinx, Altera and Lattice all seem to accept it without additional logic.
In @SteveScully voice: "Okay, thank you for your comment."
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