Update: We have released some things.https://twitter.com/oe1cxw/status/943857881270685696 …
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This is a Xilinx 7-Series CLB+Interconnect configuration segment. So far we know what all the colored bits do (92.88% atm and increasing at a steady rate). Intrigued? Come to #34C3 and talk to us at the OpenFPGA assembly (https://events.ccc.de/congress/2017/wiki/index.php/Assembly:Openfpga …).pic.twitter.com/Y6fiW0vjKG
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I will definitely pop by. There's a couple of things I'd like to do for which a Kintex-7 would be the right hardware for.
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The solid phase of magic smoke, duh.
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As a thank you for your work you have done in 2015, we try to rescue you from Tcl.
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Genuinely curious Clifford...how do you propose to do anything timing driven (STA/Synthesis/Physical Design) without the ability to extract exact values from the actual layout of the FPGA?
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Ask me at
#34c3. ;) - Show replies
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I can freely lay my paws on kc705, is there any way I can help?
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Why are people now posting this old tweet? Here is the most recent update: https://twitter.com/oe1cxw/status/943857881270685696 … We released some of the scripts and databases. So far it seems like Kintex and Artix use exactly the same bitstream format. (Virtex might have some extra interconn, idk yet.)
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Man time flies, it feels like 
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