We need a new IR language badly, but for now everything must go through verilog for tool compatibility
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Replying to @OlofKindgren @fpga_languages and
What kind of IR would you imagine? Like LLVM / WebAssembly IR?
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Replying to @wavedrom @OlofKindgren and
Imo this is a two-part problem: (1) a netlist format and (2) a standard cell library. The "industry solutions" would be EDIF and LPM. Both not very convincing solutions imo.
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Replying to @oe1cxw @OlofKindgren and
How about the IR that can capture Higher Level Verilog constructs?
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Replying to @wavedrom @OlofKindgren and
Like unelaborated functions and generate blocks? Have no place in an IR imo. Too specific to a source language. (LLVM IR doesn't preserve things like C++ templates either, and that's a good thing. You want your IR simple and language-agnostic.)
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Replying to @oe1cxw @OlofKindgren and
WebAssembly bytecode for example captures some structural features, like if-then-else, loop, switch. Also expressions. It is a bit higher then just netlist.
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Replying to @wavedrom @OlofKindgren and
But I wouldn't call them higher level constructs of any particular language. Please clarify which "Higher Level Verilog Constructs" you want to see preserved in an IR.
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Replying to @oe1cxw @OlofKindgren and
Here is an Fibonacci code in WebAssembly IR (text form): https://github.com/WebAssembly/testsuite/blob/master/fac.wast … If has: call, if-then-else, loop, expression trees, local declarations. That sort of high level.
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Replying to @wavedrom @OlofKindgren and
This doesn't answer my question. What "Higher Level VERILOG Constructs" you want to see preserved.
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Replying to @oe1cxw @OlofKindgren and
Is the (if-then-else) verilog construct higher level then netlist?
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Replying to @wavedrom @OlofKindgren and
It translate directly to $mux, so no.
11:29 AM - 19 Nov 2017
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