Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

And you're just making the case against Verilog.

does migen compile to VHDL? Does any higher level abstraction language skip VHDL / Verilog and go straight to synthesis?

We need a new IR language badly, but for now everything must go through verilog for tool compatibility

What kind of IR would you imagine? Like LLVM / WebAssembly IR?

Imo this is a two-part problem: (1) a netlist format and (2) a standard cell library. The "industry solutions" would be EDIF and LPM. Both not very convincing solutions imo.

How about the IR that can capture Higher Level Verilog constructs?

Like unelaborated functions and generate blocks? Have no place in an IR imo. Too specific to a source language. (LLVM IR doesn't preserve things like C++ templates either, and that's a good thing. You want your IR simple and language-agnostic.)

WebAssembly bytecode for example captures some structural features, like if-then-else, loop, switch. Also expressions. It is a bit higher then just netlist.