>> this scheduled other blocks, causing endless loops. Other sims were smart enough to break loops to different degrees
-
WebAssembly bytecode for example captures some structural features, like if-then-else, loop, switch. Also expressions. It is a bit higher then just netlist.
But I wouldn't call them higher level constructs of any particular language. Please clarify which "Higher Level Verilog Constructs" you want to see preserved in an IR.
-
-
Here is an Fibonacci code in WebAssembly IR (text form): https://github.com/WebAssembly/testsuite/blob/master/fac.wast … If has: call, if-then-else, loop, expression trees, local declarations. That sort of high level.
-
Looks like it shares the LISP syntax heritage with GCCs IR. Are they similar?
End of conversation
New conversation -
-
-
Keep it legal to assign from something that doesn't exist. That's my favorite verilog feature
-
You mean automatically resolved forward declarations? Those aren't universally supported in my experience, and they've caused me problems before. I now declare explicitly everything at the top of my modules.
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.