How is it not an Icarus bug? Note that most other simulators behave.
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How about the IR that can capture Higher Level Verilog constructs?
Like unelaborated functions and generate blocks? Have no place in an IR imo. Too specific to a source language. (LLVM IR doesn't preserve things like C++ templates either, and that's a good thing. You want your IR simple and language-agnostic.)
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WebAssembly bytecode for example captures some structural features, like if-then-else, loop, switch. Also expressions. It is a bit higher then just netlist.
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But I wouldn't call them higher level constructs of any particular language. Please clarify which "Higher Level Verilog Constructs" you want to see preserved in an IR.
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