Not sure I'd call it an Icarus bug, but ok, great that it works now. Built-in sim is only for pure migen designs, right?
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Replying to @OlofKindgren @oe1cxw
How is it not an Icarus bug? Note that most other simulators behave.
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Replying to @M_Labs_Ltd @oe1cxw
because (at least two years ago) Migen generated always(*) blocks that unconditionally updated signal values >>
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>> this scheduled other blocks, causing endless loops. Other sims were smart enough to break loops to different degrees
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modelsim (or vivado xsim. Don't remember) wasn't immune to this either. I had to manually fix up some generated code
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Replying to @OlofKindgren @oe1cxw
And you're just making the case against Verilog.
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does migen compile to VHDL? Does any higher level abstraction language skip VHDL / Verilog and go straight to synthesis?
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We need a new IR language badly, but for now everything must go through verilog for tool compatibility
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Replying to @OlofKindgren @fpga_languages and
What kind of IR would you imagine? Like LLVM / WebAssembly IR?
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Replying to @wavedrom @OlofKindgren and
Imo this is a two-part problem: (1) a netlist format and (2) a standard cell library. The "industry solutions" would be EDIF and LPM. Both not very convincing solutions imo.
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Netlist formats are all very easy to convert losslessly. Cell libraries (we are talking parameterized coarse grain cells here) aren't always. But for example Yosys RTLIL and Chisel FIRRTL are surprisingly similar in this regard.
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