That's an Icarus bug and it's now fixed AFAIK. Also you can use the built-in simulator.
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What kind of IR would you imagine? Like LLVM / WebAssembly IR?
Imo this is a two-part problem: (1) a netlist format and (2) a standard cell library. The "industry solutions" would be EDIF and LPM. Both not very convincing solutions imo.
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How about the IR that can capture Higher Level Verilog constructs?
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Like unelaborated functions and generate blocks? Have no place in an IR imo. Too specific to a source language. (LLVM IR doesn't preserve things like C++ templates either, and that's a good thing. You want your IR simple and language-agnostic.)
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Netlist formats are all very easy to convert losslessly. Cell libraries (we are talking parameterized coarse grain cells here) aren't always. But for example Yosys RTLIL and Chisel FIRRTL are surprisingly similar in this regard.
Thanks. Twitter will use this to make your timeline better. UndoUndo
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I guess the two hottest candidates right now are FIRRTL from Chisel and the one in Yosys.
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Would be nice to be able to externalize this format as pure data. JSON for example.
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