Usually when I get better in a programming language and/or API I also start liking it more. But Vivado TCL is so horrible, there isn't even Stockholm syndrome for it. (But I'm, glad Vivado has at least some API like this.)pic.twitter.com/5Oyhp7dwYB
Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.
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Usually when I get better in a programming language and/or API I also start liking it more. But Vivado TCL is so horrible, there isn't even Stockholm syndrome for it. (But I'm, glad Vivado has at least some API like this.)pic.twitter.com/5Oyhp7dwYB
All that just for a darn non-inverting loop? Silly question: why not just Verilog? Does it not map to the same?
I need to query the device database to figure out where to LUT must go and what input to use. Once I have this information I could as well use Verilog to create the cell and net, but that wouldn't make it any simpler imo (and would be much slower).
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