language: verilog time to triangle: 3 days a python script turns the vcd into an imagepic.twitter.com/sueOzocEO0
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iverilog doesn't accept my code (PARAM'b0) but also it's reassuring that this way graphviz and sim go through the same frontend
Jfyi that syntax is a Yosys extension, in Verilog that's actually not allowed. The standard Verilog way of creating a zero of parameterized length is {PARAM{1'b0}}. But please keep testing my simulator. ^_^
