language: verilog time to triangle: 3 days a python script turns the vcd into an imagepic.twitter.com/sueOzocEO0
Show this thread
Oh wow! I'm not complaining but.. why not use iverilog for simulation? :) There are not many users of the "sim" command in Yosys. We might very well be the only two. So please don't hesitate to ping me if you find something that might be a bug.
-
-
iverilog doesn't accept my code (PARAM'b0) but also it's reassuring that this way graphviz and sim go through the same frontend
-
Jfyi that syntax is a Yosys extension, in Verilog that's actually not allowed. The standard Verilog way of creating a zero of parameterized length is {PARAM{1'b0}}. But please keep testing my simulator. ^_^
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.