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Hi @oe1cxw ,
I am trying to synthesize SPI standalone code using yosys. I correctly simulated with Icarus w/ correct outputs. But yosys prints this error(copied in readme file) for multiple edge sensitive events for a signal.
Code & error file here:https://github.com/hgpurswani/spi_adc_interface.git …
This is not synthesizeable code.The case..endcase must be in an else branch in this case. See 5.2.2.1 of IEEE Std 1364.1-2002.pic.twitter.com/pqcNSoKGc2
not sure if related: I see registers which are only assigned along certain paths, which is IME something the Verilog tools don't really like; also the block is written like it were a combinatorial block?... (granted, I am sort of a newb to VL, so dunno).
Hi, As @oe1cxw said, case..endcase was not in an else branch. After doing this, it worked.
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