The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
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Replying to @oe1cxw
Orca, ri5cy, rocket, Sodor, ridecore, boom, SCR1, Shakti, zscale, picorv32, rv12, falcon, mi-v, rv64g, vsxale ...? :)
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Replying to @oe1cxw @OlofKindgren
Presumably one that has something to do with MIT. ;-)
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Replying to @RichFelker @OlofKindgren
Nope. Wrong coast. :) But this "writing to misa CSR" thing is also a hot topic in the riscv formal spec workgroup right now..
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...is the RISC-V spec about to get a notion of UNPREDICTABLE behavior? :P
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Replying to @erincandescent @oshepherd and
In the memory model: sure. But not with this. This is simply implementation defined.
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Imp def to do what? When is the write guaranteed to be observed? What are the behavioral restrictions between the write and then?
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Replying to @erincandescent @oshepherd and
Spec behavior is to trigger a unaligned instr trap for the next instruction.
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Replying to @oe1cxw @oshepherd and
Impl defined is if writes to misa reg can be used to enable/disable ISA extensions.
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An implementation can also simply have all extensions always enabled and ignore misa writes. (Or only support it for some extensions.)
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