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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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      The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..

      4 replies 1 retweet 4 likes
    2. Olof Kindgren‏ @OlofKindgren 21 Oct 2017
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      Replying to @oe1cxw

      Orca, ri5cy, rocket, Sodor, ridecore, boom, SCR1, Shakti, zscale, picorv32, rv12, falcon, mi-v, rv64g, vsxale ...? :)

      3 replies 0 retweets 1 like
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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      Replying to @OlofKindgren

      Yes. It's one of those. :)

      1 reply 0 retweets 2 likes
    4. Rich Felker‏ @RichFelker 21 Oct 2017
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      Replying to @oe1cxw @OlofKindgren

      Presumably one that has something to do with MIT. ;-)

      1 reply 0 retweets 1 like
    5. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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      Replying to @RichFelker @OlofKindgren

      Nope. Wrong coast. :) But this "writing to misa CSR" thing is also a hot topic in the riscv formal spec workgroup right now..

      2 replies 0 retweets 0 likes
    6. Erin  ✨ 💽‏ @erincandescent 21 Oct 2017
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      Replying to @oe1cxw @RichFelker @OlofKindgren

      ...is the RISC-V spec about to get a notion of UNPREDICTABLE behavior? :P

      1 reply 0 retweets 2 likes
    7. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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      Replying to @erincandescent @oshepherd and

      In the memory model: sure. But not with this. This is simply implementation defined.

      1 reply 0 retweets 0 likes
    8. Erin  ✨ 💽‏ @erincandescent 21 Oct 2017
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      Replying to @oe1cxw @RichFelker @OlofKindgren

      Imp def to do what? When is the write guaranteed to be observed? What are the behavioral restrictions between the write and then?

      1 reply 0 retweets 1 like
    9. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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      Replying to @erincandescent @oshepherd and

      Spec behavior is to trigger a unaligned instr trap for the next instruction.

      2 replies 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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      Replying to @oe1cxw @oshepherd and

      Impl defined is if writes to misa reg can be used to enable/disable ISA extensions.

      11:24 AM - 21 Oct 2017
      1 reply 0 retweets 0 likes
        1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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          Replying to @oe1cxw @oshepherd and

          An implementation can also simply have all extensions always enabled and ignore misa writes. (Or only support it for some extensions.)

          0 replies 0 retweets 0 likes
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