The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
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Imp def to do what? When is the write guaranteed to be observed? What are the behavioral restrictions between the write and then?
Spec behavior is to trigger a unaligned instr trap for the next instruction.
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Impl defined is if writes to misa reg can be used to enable/disable ISA extensions.
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An implementation can also simply have all extensions always enabled and ignore misa writes. (Or only support it for some extensions.)
End of conversation
New conversation -
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*CPU designers immediately rewrite all their CPUs to make writes to this register cause an immediate pipeline flush*
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