The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
-
-
Replying to @oe1cxw
Orca, ri5cy, rocket, Sodor, ridecore, boom, SCR1, Shakti, zscale, picorv32, rv12, falcon, mi-v, rv64g, vsxale ...? :)
3 replies 0 retweets 1 like -
-
Replying to @oe1cxw @OlofKindgren
Presumably one that has something to do with MIT. ;-)
1 reply 0 retweets 1 like -
Replying to @RichFelker @OlofKindgren
Nope. Wrong coast. :) But this "writing to misa CSR" thing is also a hot topic in the riscv formal spec workgroup right now..
2 replies 0 retweets 0 likes -
Replying to @oe1cxw @OlofKindgren
Seems like a stupid bikeshed to me. It shouldn't even be writable.
2 replies 0 retweets 0 likes -
For virt/priv control, a higher priv domain should perhaps be able to limit features in guest. But never change its own state.
1 reply 0 retweets 0 likes
Replying to @RichFelker @OlofKindgren
This is also done with this. There is only one misa CSR, not one per priv level.
11:21 AM - 21 Oct 2017
0 replies
0 retweets
0 likes
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.