The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
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...is the RISC-V spec about to get a notion of UNPREDICTABLE behavior? :P
In the memory model: sure. But not with this. This is simply implementation defined.
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Imp def to do what? When is the write guaranteed to be observed? What are the behavioral restrictions between the write and then?
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Spec behavior is to trigger a unaligned instr trap for the next instruction.
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