The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
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Presumably one that has something to do with MIT. ;-)
Nope. Wrong coast. :) But this "writing to misa CSR" thing is also a hot topic in the riscv formal spec workgroup right now..
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...is the RISC-V spec about to get a notion of UNPREDICTABLE behavior? :P
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In the memory model: sure. But not with this. This is simply implementation defined.
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