The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
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The "misa" CSR may be writeable to enable/disable parts of the ISA ("may" bc its optional, a core does not need to support that).
This can be used for ex to (a) test SW written for a smaller ISA or (b) reduce task switch overhead (for exts that add additional state).