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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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    Examples of bugs found by riscv-formal:https://github.com/cliffordwolf/riscv-formal/blob/master/docs/examplebugs.md …

    6:02 AM - 21 Oct 2017
    • 22 Retweets
    • 38 Likes
    • Oscar Barenys Befedo Lee Fisher Mark Eichin chuck io:r//us Ram krishna mahat Real AI Adrian Rueegsegger Yann Sionneau
    2 replies 22 retweets 38 likes
      1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Oct 2017
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        I think this divider reset issue is my favorite bug I've found with riscv-formal so far. Which processor? Here's a hint: A tiny RV32. :)pic.twitter.com/3lYiYoPeQg

        1 reply 1 retweet 9 likes
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      1. OSS FPGA & ASIC EDA tools‏ @ico_TC 21 Oct 2017
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        Replying to @oe1cxw

        I think we should start collecting of "my favorite chip design bug". Like " Hello, my name is Dan. I am chip designer. I produce bugs."

        0 replies 0 retweets 2 likes
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