RV64? This is something we’re contemplating as well. Although, we’ll implement some assembler fixups for alignment.
The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
-
-
-
This was on a core that is compile-time configurable as RV32/RV64, but so far I only looked at the RV32 variant.
End of conversation
New conversation -
-
-
I am half wondering how RISC-V's compressed ISA compares with my own 16/32 RISC ISA project, but comparing seems like a lot of effort...
-
mine had gone the other way, basically tacking a bunch of 32-bit instruction-forms onto a variant of the Hitachi SH4 ISA; so a bit different
End of conversation
New conversation -
-
-
Orca, ri5cy, rocket, Sodor, ridecore, boom, SCR1, Shakti, zscale, picorv32, rv12, falcon, mi-v, rv64g, vsxale ...? :)
-
Definitely not KCP53000; I don't support C-extension. ;)
- Show replies
New conversation -
-
-
Wait, why is compressed ISA something you enable/disable and not just something that always works on CPUs that support it?!?
-
Or do you mean something like jumping from compressed-isa code to 32-bit isa code where the jump insn isn't 32-bit aligned?
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.