what the hell
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Replying to @whitequark
Best thing is: The MIT model has at least one bug that riscv-formal would catch immediately. But they don't know that because they 1/2
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Replying to @oe1cxw @whitequark
have not formally verified their model against ANYTHING yet. I'm not telling them bc I want to "find it with riscv-formal" first. :) 2/2
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Replying to @oe1cxw @whitequark
But I can't yet. Because so far they can't interface their model with anything that would actually allow me to use formal methods on it..
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Replying to @oe1cxw @whitequark
You’re saying there is a bug in the spec they are verifying against?
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Replying to @alastair_d_reid @whitequark
Yes. But they aren't verifying their spec against anything (yet). Their primary focus is on proofing abstract properties of the ISA..
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And that is also very important of course, but I think the first step should be proving that the spec actually matches the implementation.
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Replying to @oe1cxw @whitequark
But but but... all the hard bits of specs and of processors are in exception handling. If you skip that bit, you’re doing the easy 10%
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Replying to @alastair_d_reid @whitequark
This is the MIT Spec: https://github.com/mit-plv/riscv-semantics … Contains parser for subset of Haskell with >200 shift-reduce (and some r-r) conflicts.
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It's pretty much decided now that this will be the basis for the official RISC-V formal spec, replacing riscv-isa-sim as golden reference.
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I have formally verified my spec against the C code in riscv-isa-sim. I fear that there will be a verification gap with this new spec..
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But I can see a lot of potential in the Haskell spec as well. I just think it's nowhere near ready yet.
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Let's make risc-v formal the defacto standard which most real chip designers use because it is more useful to them to find bugs ;-)
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