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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 6 Oct 2017
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      Working on extending riscv-formal to support the M ISA extension. Already found a reset bug in PicoRV32 divider control logic.

      1 reply 2 retweets 14 likes
    2. Niels Moseley‏ @trc_wm 6 Oct 2017
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      Replying to @oe1cxw

      Any chance of writing a paper on the subject? #PhD.

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 6 Oct 2017
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      Replying to @trc_wm

      Yeah, I really should. I'll put in on the todo list..

      9:23 AM - 6 Oct 2017
      • 1 Like
      • Niels Moseley
      1 reply 0 retweets 1 like
        1. OSS FPGA & ASIC EDA tools‏ @ico_TC 6 Oct 2017
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          Replying to @oe1cxw @trc_wm

          just consider it a whitepaper for your sales team ....

          0 replies 0 retweets 1 like
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