Pushing about 8000 lines of new Verilog through Quartus. Most common typos? Trailing/missing commas and missing periods in module instances.
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Will Verilator accept non-synthesizable constructs? Or can those be disabled for checking? Never tried recursive modules, yet...
Verilator almost only accepts synthesizable Verilog. But afaik there is no switch for restricting it to a pure synthesis subset.
