Pushing about 8000 lines of new Verilog through Quartus. Most common typos? Trailing/missing commas and missing periods in module instances.
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What's your process here? Writing thousands of lines of code in one sitting and then straight to synthesis without prior simulation? 
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Not quite. I run code through synthesis first to find syntax errors and design errors a simulator would not notice (Modelsim especially!)
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This also shows stuck-at warnings and hierarchy connectivity errors. I can then compare the RTL diagram against the orig design schematic.
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Those 8793 lines were written as a side-project over more than a year, split across about 88 modules. LOTS of schematics prior to that.
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