@johnregehr I just watched your 2014 talk on Souper at UW on YouTube. Fascinating how similar it is (was at the time) to "freduce" in Yosys.
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Then I create SAT instances to see if they actually are the same. If not I use the counter example as additional simulation input to..
.. break other pairs that are still marked as candidates, then I create a SAT instance for the next candidate pair, and so on.
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There is some additional handling for when to signals are the exact opposite, then I replace one with the inverse of the other.
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There is also some special handling for constant zero and constant one.
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