Why there are no clock input breakouted on the @latticesemi IceStick, it's a shame especially with such a limited output range in the PLL !
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I'm interested in using an external clock directly because the pll range doesn't fit my need.
You can also route any signal (pin or internal logic) to any of the 8 global clock nets. Re range: What target frequency do you need?
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4.8MHz but clean one if I get the manual correctly I'll have to expected 500ps jitter
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To expect
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http://www.latticesemi.com/en/Support/AnswerDatabase/2/4/7/2475 … see the HOLD_MARGIN they add
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