@Obijuan_cube Can you implement fizzbuzz with icestudio?
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I have a more detailed description of the problem when we spoke in person.. :)
*gave. ASCII output (Fizz, Buzz, decimal numbers), strictly one byte per cycle without idle cycles.
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Generate at least the fist 1000 output lines (otherwise ROM table is the obvious solution).
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Here is a pre-synthesized reference implementation (pre-syn so it does not spoil the challenge): http://svn.clifford.at/handicraft/2017/fizzbuzz/ …
#Verilog#FizzBuzz
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