Yosys can now also operate as simulator, generate VCD files and use last sim state as new design init state:https://www.reddit.com/r/yosys/comments/6ulm3m/new_simulation_within_yosys/ …
Replying to @Palsenberg
The simulator is language agnostic. Any method for using VHDL for synthesis also works with the simulator.
6:27 AM - 19 Aug 2017
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