Yosys can now also operate as simulator, generate VCD files and use last sim state as new design init state:https://www.reddit.com/r/yosys/comments/6ulm3m/new_simulation_within_yosys/ …
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Replying to @oe1cxw
Interesting indeed. I see clk reset gen but how to provide other inputs? Do you've an example please?
2 replies 1 retweet 1 like -
Maybe you support synthesisable testbenches ?
1 reply 1 retweet 2 likes
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