Hmmm, I think I know a potential use case for the simulator to detect an (already-fixed) bug. Is the idea that sometimes a long chain of >>
Yosys can now also operate as simulator, generate VCD files and use last sim state as new design init state:https://www.reddit.com/r/yosys/comments/6ulm3m/new_simulation_within_yosys/ …
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states are accessible exactly once (after the reset signal) and we should skip them when determining whether a property holds generally?
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Heh,
@azonenberg and I actually discussed doing this but decided it wasn't high priority. Thanks for implementing it.Thanks. Twitter will use this to make your timeline better. UndoUndo
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ok, so I need to add a FuseSoC yosys simulator backend now. Does it support non-synthesisable code or VPI/DPI?
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No VPI/DPI and only synthesizable Verilog is supported.
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Interesting indeed. I see clk reset gen but how to provide other inputs? Do you've an example please?
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Maybe you support synthesisable testbenches ?
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Any VHDL support planned ?
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The simulator is language agnostic. Any method for using VHDL for synthesis also works with the simulator.
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