@rqou_ "yosys's verilog frontend accepts all kinds of bullshit that's invalid"
Luckily there is its sourcecode for everyone to improve it.
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https://github.com/azonenberg/openfpga/wiki/Linter-notes … is my list of things to make it complain about. Just need time to implement them...
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* Use of = in clocked always block is prohibited. * Use of <= in combinatorial always block is prohibited. Never use <= in comb blocks.pic.twitter.com/mRG0ATKGMH
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or better: never use Verilog.
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Replying to @M_Labs_Ltd @oe1cxw and
I will throw a big party on the day when we all agree that we have overcome this Verilog versus VHDL argument !
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Replying to @ico_TC @M_Labs_Ltd and
Then we can move on to arguing about using emacs or vi to write it.
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I will not rest until everyone is using ABEL and TECO, and I will achieve this by "winning" arguments on the internet !!!!11eleven
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