@rqou_ "yosys's verilog frontend accepts all kinds of bullshit that's invalid"
Luckily there is its sourcecode for everyone to improve it.
From "help read_verilog". Use an external linter if you need one, for example "verilator --lint-only".pic.twitter.com/AXLGnwWhbg
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a linter mode for FuseSoC has been on my Todo list for a while. I sometimes use --build-only for linting today
Thanks. Twitter will use this to make your timeline better. UndoUndo
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The problem with this (as you know) is that the external linter uses a different parser and supports a different subset of the language
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If it's any help, the parser front-end for Quartus/Vivado/ISE is by Verific. So that defines FPGA support for HDLs. http://www.verific.com/
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