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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. OSS FPGA & ASIC EDA tools‏ @ico_TC 8 Aug 2017
      • Report Tweet
      • Report NetzDG Violation

      @rqou_ "yosys's verilog frontend accepts all kinds of bullshit that's invalid" Luckily there is its sourcecode for everyone to improve it.

      2 replies 0 retweets 1 like
    2. Andrew Zonenberg‏ @azonenberg 8 Aug 2017
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      Replying to @ico_TC @rqou_

      https://github.com/azonenberg/openfpga/wiki/Linter-notes … is my list of things to make it complain about. Just need time to implement them...

      1 reply 2 retweets 4 likes
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 8 Aug 2017
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      Replying to @azonenberg @ico_TC @rqou_

      * Use of = in clocked always block is prohibited. * Use of <= in combinatorial always block is prohibited. Never use <= in comb blocks.pic.twitter.com/mRG0ATKGMH

      3 replies 2 retweets 4 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 8 Aug 2017
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      Replying to @oe1cxw @azonenberg and

      See also: Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!, SNUG-2000, Clifford E. Cummings http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf …

      3:17 AM - 8 Aug 2017
      • 1 Retweet
      • 4 Likes
      • Pramode C.E Aredsail Matt abrocat OSS FPGA & ASIC EDA tools
      0 replies 1 retweet 4 likes

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