@rqou_ "yosys's verilog frontend accepts all kinds of bullshit that's invalid"
Luckily there is its sourcecode for everyone to improve it.
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https://github.com/azonenberg/openfpga/wiki/Linter-notes … is my list of things to make it complain about. Just need time to implement them...
* Use of = in clocked always block is prohibited. * Use of <= in combinatorial always block is prohibited. Never use <= in comb blocks.pic.twitter.com/mRG0ATKGMH
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See also: Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!, SNUG-2000, Clifford E. Cummings http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf …
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or better: never use Verilog.
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I will throw a big party on the day when we all agree that we have overcome this Verilog versus VHDL argument !
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VHDL does this in a way which is still obnoxious, but at least isn't a footgun.
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