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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Fabian Giesen‏ @rygorous 4 Aug 2017
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      I folded and got myself a small FPGA to play with (not planning to do a CPU as is the cliche :), mumble mumble systolic arrays).

      4 replies 0 retweets 17 likes
    2. Fabian Giesen‏ @rygorous 4 Aug 2017
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      Replying to @rygorous

      I learned a tiny bit of VHDL at university, didn't like it much, so this time around I tried Verilog!

      4 replies 1 retweet 0 likes
    3. Fabian Giesen‏ @rygorous 4 Aug 2017
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      Replying to @rygorous

      Short version: I went from "Ooooh, Verilog" to "Oh dear, Verilog" within about 3 hours this Wednesday.

      9 replies 1 retweet 35 likes
    4. Kevin‏ @ElectronicKiwi 4 Aug 2017
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      Replying to @rygorous

      Did you check out Chisel (https://chisel.eecs.berkeley.edu/ ). Everyone around me in the lab seems to be using it.

      5 replies 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Aug 2017
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      Replying to @ElectronicKiwi @rygorous

      I think it's a good idea to learn Verilog first. Using a Chisel flow without understanding the generated vlog code can be challenging..

      2:31 AM - 5 Aug 2017
      0 replies 0 retweets 0 likes

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