Not sure I'd call it an Icarus bug, but ok, great that it works now. Built-in sim is only for pure migen designs, right?
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This "special functionality" is perfectly reasonable. If it doesn't have it then it can bite you randomly in manually written code as well.
Yes you can manually write buggy code that is broken because it relies on undefined behavior. What's your point?
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Assigning its current value to a signal should not trigger always blocks. Built-in simulator (and others) do that, and things work.
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Yes, that's in the Verilog standard. But that's not a special "loop detection and breaking" feature. It's just the std behavior.
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