Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

And you're just making the case against Verilog.

verilog has many flaws, but precisely because of that, a new HDL should hide these flaws from the user, not expose them

Just don't use poor Verilog simulators.

Just don't generate Verilog code that only works with simulators that provide special functionality above and beyond the language spec. :)

And synthesizers must already implement something like that. Is it actually not in the Verilog spec? Then the spec should be fixed.

There is certainly nothing in the Vlog std about detecting and breaking loops. Nor should there be. 1/6

And I seriously doubt that any tool does anything like that. Much more likely: Your code loops if events are 2/6

popped from the active queue in one particular order, and doesn't loop with another order. But the spec says 3/6