Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

because (at least two years ago) Migen generated always(*) blocks that unconditionally updated signal values >>

>> this scheduled other blocks, causing endless loops. Other sims were smart enough to break loops to different degrees

modelsim (or vivado xsim. Don't remember) wasn't immune to this either. I had to manually fix up some generated code

And you're just making the case against Verilog.

verilog has many flaws, but precisely because of that, a new HDL should hide these flaws from the user, not expose them

Just don't use poor Verilog simulators.

Just don't generate Verilog code that only works with simulators that provide special functionality above and beyond the language spec. :)

And synthesizers must already implement something like that. Is it actually not in the Verilog spec? Then the spec should be fixed.