Not sure I'd call it an Icarus bug, but ok, great that it works now. Built-in sim is only for pure migen designs, right?
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And synthesizers must already implement something like that. Is it actually not in the Verilog spec? Then the spec should be fixed.
There is certainly nothing in the Vlog std about detecting and breaking loops. Nor should there be. 1/6
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And I seriously doubt that any tool does anything like that. Much more likely: Your code loops if events are 2/6
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popped from the active queue in one particular order, and doesn't loop with another order. But the spec says 3/6
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