otoh, last time I checked, Migen generated verilog that couldn't be run in Icarus because of infinite event loops
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Just don't use poor Verilog simulators.
Just don't generate Verilog code that only works with simulators that provide special functionality above and beyond the language spec. :)
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This "special functionality" is perfectly reasonable. If it doesn't have it then it can bite you randomly in manually written code as well.
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Yes you can manually write buggy code that is broken because it relies on undefined behavior. What's your point?
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And synthesizers must already implement something like that. Is it actually not in the Verilog spec? Then the spec should be fixed.
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synthesizers have no notion of time, which makes things quite different from simulation in this case
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As much as Linux had to surpass POSIX in the past to go forward, Yosys will need to extend standard Verilog one day for the better.
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Let's hope not, because that's what leads to things like https://twitter.com/oe1cxw/status/892324939835027456 … :)
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