Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

3.2.2 says reg decl with val should be treated "as if the assignment occurred in a blocking assignment in an initial construct" ...

Which LRM are you reading? IEEE-1364-2005 3.2 is about whitespaces, IEEE-1800-2009 3.2 is about "design elements" (modules, checker, ..).

Neither has a section 3.2.2. But you are right: init value is like initial block. Don't need to check LRM for that.

But this is not the question: The question is if in the Verilog stratified event queue model it is guaranteed that an always block >>

is scheduled in the inactive queue in response to an initial clock condition after all propagated initial values have been put into >>

the active queue. If propagated initial values and triggered always block ever can be in the same queue then order isn't guaranteed >>

which means that the always block can sample a signal effected by initial values before initial values propagated completely.

need to eat and think about this :) sv at least old 3.1a) seems to be more explicit.